The advent of the integrated circuit has had a significant impact on various types of communication devices. The integrated circuit has been incorporated into both radio frequency applications and high speed communication network systems. While operation speeds of these communication devices have dramatically increased, the demand for yet faster communication devices continues to rise. Thus, the semiconductor manufacturing industry continually strives to increase the overall speed of the integrated circuit. One way in which the semiconductor industry has increased the speed of the integrated circuit is to continue to shrink the size of the transistor. Over the last few years, the device size of the transistor has gone from 0.5 μm to 0.32 μm to 0.25 μm and now transistor device sizes are heading to the 0.18 μm range and below. As transistor device sizes have continued to dramatically decrease, with each decrease in size the semiconductor industry has faced new challenges.
One such challenge is that of eliminating parasitic capacitance as much as possible. This is particularly the case in communication devices and communication network systems in general. One integrated circuit component that is often incorporated into these communication devices and networks, is the bipolar transistor. The bipolar transistor facilitates the faster operating speeds that are needed for complex communication network systems because of its inherent ability to switch higher current loads at high speed. However, as device sizes have continued to shrink into the sub-micron size, bipolar transistor scaling has become difficult due to the increased parasitic capacitance per unit area associated with the higher doping levels required for these devices. For example, in some cases, emitter base parasitic capacitance (CEBP) can be as high as 60% of the total emitter base capacitance (CEB), which severely slows down emitter coupled logic (ECL) type circuits, which are often used in high-speed communication network systems.
The industry has attempted to solve this problem by producing a smaller emitter base overlap to reduce CEBP. However, the production of this device often requires more advanced and expensive photolithographic tools. Moreover, increased variability in device parameters can reduce design flexibility and reduce cost. In addition, non-ideal emitter base recombination current can severely degrade device performance.
Another challenge is “cross-talk.” As is well known, cross-talk results when electrical noise, which is often a product of the higher current levels associated with bipolar devices, travels through the capacitive coupling of the substrate and negatively affects the performance of other devices located nearby. Though cross-talk has been a well known phenomenon, up until recently it was of less concern. However, as a result of the use of multi-gigahertz operating frequencies in today's RF devices, the significance of cross-talk has increased dramatically. In addition, with the increase in packing density and decrease in device size, bipolar devices and other transistor devices are being manufactured on the same chip with tighter spacing, which increases the relative importance of the cross-talk problem. Thus, as a result of the increased packing density and the decreased device sizes, both taken in conjunction with the cross-talk problems, device performance and integration issues are becoming increasingly apparent.
Accordingly, what is needed in the art is a bipolar transistor and a method of manufacture thereof, that significantly reduces the parasitic capacitance and “cross-talk” problems associated with the prior art bipolar transistors.